@conference {1354036,
title = {Static variable ordering in ZBDDs for path delay fault coverage calculation},
booktitle = {MWSCAS {\textquoteright}04: The 2004 47th Midwest Symposium on Circuits and Systems},
volume = {1},
year = {2004},
pages = {I-497-500 vol.1},
abstract = {Zero-suppressed binary decision diagrams (ZBDDs) are data structures that represent sets efficiently and they have recently been suggested for use in nonenumerative path delay fault (PDF) coverage calculations. Many heuristics have been proposed to order variables (representing primary inputs) in ZBDDs to avoid size explosion; however, in ZBDD-based PDF coverage calculations, the variables represent the nets in a circuit, not the circuit primary inputs. This fact motivates us to investigate new ordering strategies since the number of nets in a circuit is relatively large as compared to the number of primary inputs. Several new static ordering heuristics are proposed based on structural properties of the circuit undergoing PDF coverage calculations and are evaluated. The experimental results show that the new heuristics we propose greatly reduce the size of the ZBDDs.},
keywords = {binary decision diagrams, Circuit faults, circuit testing, combinational circuits, Data structures, Delay, fault location, Flip-flops, logic testing, path delay fault coverage calculation, Programmable logic arrays, Programmable logic devices, Sequential analysis, sequential circuits, static variable ordering heuristics, structural properties, VLSI, VLSI circuits, zero suppressed binary decision diagrams},
doi = {10.1109/MWSCAS.2004.1354036},
author = {Kocan, Fatih and Gunes, Mehmet Hadi and Thornton, Mitchell A.}
}