Sat, 2013-06-15 01:50 — mgunes

Title | On the ZBDD-based nonenumerative path delay fault coverage calculation |

Publication Type | Journal Article |

Year of Publication | 2005 |

Authors | Kocan F, Gunes MH |

Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |

Volume | 24 |

Pagination | 1137-1143 |

ISSN | 0278-0070 |

Keywords | circuit analysis computing, circuit complexity, Circuit faults, Circuit simulation, circuit testing, combinational circuits, Data structures, Delay effects, fault diagnosis, Fault grading, logic partitioning, logic testing, nonenumerative path delay fault coverage calculation, Partitioning algorithms, path delay fault (PDF), path delay fault grading algorithms, Sequential analysis, simulation, time complexity, Timing, Very large scale integration, ZBDD |

Abstract | We devise one exact and one pessimistic path delay fault (PDF) grading algorithms for combinational circuits. The first algorithm, an extension to the basic grading algorithm of Padmanaban, Michael, and Tragoudas (2003), does not store all of the detected PDFs during the course of grading, and, as a further improvement, it utilizes compressed representation of PDFs. These two techniques yield a space-and-time efficient algorithm. To enable grading of circuits with exponential number of paths, a circuit is first partitioned into a set of subcircuits. The second algorithm efficiently calculates the coverage of partitioned circuits. The former algorithm results in 50%-70% reduction in space and a speedup from 1.6 to 2.48 in ISCAS85 benchmarks. The time complexity of the latter algorithm is O(N2) subset operations per test vector where N is the number of nets in the circuit. |

DOI | 10.1109/TCAD.2005.850851 |